1. Field of the Invention
The present invention relates to a data decoding circuit for regenerating a bit synchronization signal from a data received by using a code such as-split-phase code and Manchester code in which a binary value can be detected through a transition of voltage at a central area of a bit cell and for transforming the received data into a serial binary data.
2. Description of the Related Art
To decode a data of split-phase code, Manchester code or the like, the prior art takes the following procedure. The edge of a received data is first detected by an edge detecting circuit, the output of which is then used to form a bit synchronization signal. A serial binary data was obtained by sampling the received data with the bit synchronization signal.
The bit synchronization signal was formed by a bit synchronization circuit which used a digital or analog phase-locked loop circuit.
One digital phase-locked loop circuit is described in Japanese Patent Application Laid-Open No. 60-227541 while one analog phase-locked loop circuit is described in Japanese Patent Application Laid-Open No. 5-14333.
The other references such as Japanese Patent Application Laid-Open No. 63-191433 and Japanese Patent Publication No. 3-3429 also describe a bit synchronization circuit for obtaining a bit synchronization signal.
When the split-phase code or Manchester code is to be decoded, there are following important conditions for that.
(1) Synchronism recovery time (or the number of data bits required to recover the synchronism) must be reduced when a data for a frame synchronization signal (or preamble data) is received (Japanese Patent Publication No. 3-3429).
(2) Synchronization must not be disturbed when the same data (e.g., one) is continuously inputted info a transferred data (Japanese Patent Application Laid-Open No. 62-241435 or Japanese Patent Application Laid-Open No. 5-14333).
(3) An encoded received data must be capable of being decoded even if it contains a jitter which may be .+-.18 nsec. at a transfer frequency of 10 MHz in a network according to IEEE 802.3 Standard (Japanese Patent Application Laid-Open No. 60-227541).
(4) The data decoding circuit can be formed easily as a semiconductor device (Japanese Patent Application Laid-Open No. 60-227541, Japanese Patent Publication No. 3-3429 or Japanese Patent Application Laid-Open No. 5-14333).
In order to code a data to be transmitted according to a standard and to transmit the encoded data, the data transmission uses a medium for propagating the encoded data, a transmitter for driving the data propagation medium and a receiver for receiving the encoded data through the medium and for decoding the received data at a receiving circuit to regenerate the original data.
In the prior art, the data decoding circuit digitizes a received return-to-zero (RZ) data at the receiving circuit to sample directly with a bit synchronization signal. The receiving circuit is thus required to reproduce exactly the pulse width, cycle and others of the received data. In other words, they are required to increase the response speed of a comparator used in the receiving circuit and also to bring the offset of the comparator near to zero as much as possible.
Such requirements raised problems in that, the current consumption is increased and that the circuit is increased in scale to make the semiconductor device more expensive.
When the data decoding circuit is formed as a semiconductor device, voltage-controlled oscillation circuit is normally used. It is desirable that even if the oscillation frequency of the voltage-controlled oscillation circuit is lowered, phase synchronization can be accomplished with a high precision.